SYNOPSYS, INC.
Patent Owner
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- US PATENTS IN FORCE 2,236
- 209 US APPLICATIONS PENDING
- Feb 01, 2018 most recent publication
Details
- 2,236 Issued Patents
- 353 Issued in last 3 years
- 182 Published in last 3 years
- 43,738 Total Citation Count
- May 09, 1983 Earliest Filing
- 176 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
20082009201020112012201320142015201620172018
0100200
Technologies
Intl Class
Technology
MATTERS
Rank in Class
Top Patents (by citation)
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Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2018/0032,448
Guarded Memory Access in a Multi-Thread Safe System Level Modeling Simulation
Oct 10, 17
Feb 01, 18
[G06F]
2018/0033,795
One-Time Programmable Bitcell with Native Anti-Fuse
Jul 27, 17
Feb 01, 18
[G11C, H01L]
2018/0004,862
Optimizing The Ordering Of The Inputs To Large Commutative-Associative Trees Of Logic Gates
Jun 22, 17
Jan 04, 18
[G06F]
2018/0004,876
Reset Domain Crossing Management Using Unified Power Format
Jun 26, 17
Jan 04, 18
[G06F]
2018/0004,877
Method and Apparatus for Collecting Signal Values in FPGA Based Emulation Machine
May 16, 17
Jan 04, 18
[G06F, H03K]
2018/0005,707
Logic Timing and Reliability Repair for Nanowire Circuits
Jun 27, 17
Jan 04, 18
[G11C, G06F, H01L, H03K]
2018/0005,708
Enhancing Memory Yield and Performance Through Utilizing Nanowire Self-Heating
Jun 27, 17
Jan 04, 18
[G11C, G06F, H01L]
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
9870442
Equivalence checking between two or more circuit designs that include square root circuits
Sep 21, 15
Jan 16, 18
[G06F]
9865334
Efficient bitline driven one-sided power collapse write-assist design for SRAMs
Dec 02, 16
Jan 09, 18
[G11C]
9857409
Negative bias thermal instability stress testing of transistors
Aug 15, 14
Jan 02, 18
[G01R]
9860055
Flexible architecture for processing of large numbers and method therefor
Mar 22, 07
Jan 02, 18
[H04L, G06F, G07F]
9852242
Atomic scale grid for modeling semiconductor structures and fabrication processes
Sep 05, 14
Dec 26, 17
[G05B, G06F]
Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
2016/0342,727
METHOD AND SYSTEM FOR CHECKING AND CORRECTING SHOOT-THROUGH IN RTL SIMULATION
ABAN
May 19, 15
Nov 24, 16
[G06F]
2016/0335,387
Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips
ABAN
Jul 28, 16
Nov 17, 16
[G06F]
2016/0154,902
Selective Annotation Of Circuits For Efficient Formal Verification With Low Power Design Considerations
ABAN
Jan 14, 15
Jun 02, 16
[G06F]
2016/0063,162
SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW
ABAN
Jul 29, 15
Mar 03, 16
[G06F]
2015/0379,186
SYSTEM AND METHOD FOR GRADING AND SELECTING SIMULATION TESTS USING PROPERTY COVERAGE
ABAN
Jun 22, 15
Dec 31, 15
[G06F]
2015/0248,363
MULTI MODE ADDRESS SPACES FOR PC TO DEVICE TRANSFER OPTIMIZATION
ABAN
Feb 26, 15
Sep 03, 15
[G06F]
2015/0234,973
SYSTEM AND METHOD FOR ABSTRACTION OF A CIRCUIT PORTION OF AN INTEGRATED CIRCUIT
ABAN
Feb 14, 14
Aug 20, 15
[G06F]
2015/0143,307
SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN
ABAN
Mar 04, 14
May 21, 15
[G06F]
2015/0089,465
SEPARATION AND MINIMUM WIRE LENGTH CONSTRAINED MAZE ROUTING METHOD AND SYSTEM
ABAN
Sep 25, 14
Mar 26, 15
[G06F]
2015/0063,010
NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING FOR STATIC RANDOM ACCESS MEMORY (SRAM)
ABAN
Aug 15, 14
Mar 05, 15
[G11C]
2014/0346,634
ON-CHIP INDUCTORS WITH REDUCED AREA AND RESISTANCE
ABAN
May 23, 13
Nov 27, 14
[G06F, H01L]
2014/0282,322
SYSTEM AND METHOD FOR FILTRATION OF ERROR REPORTS RESPECTIVE OF STATIC AND QUASI-STATIC SIGNALS WITHIN AN INTEGRATED CIRCUIT DESIGN
ABAN
Apr 29, 13
Sep 18, 14
[G06F]
Top Inventors for This Owner
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