Enhancing memory yield and performance through utilizing nanowire self-heating
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United States of America Patent
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Aug 13, 2019
Grant Date -
Jan 4, 2018
app pub date -
Jun 27, 2017
filing date -
Jul 1, 2016
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Abstract
A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating. The method can comprise determining a memory cell that has a read current below a passing criteria, the memory cell having a transistor with a nanowire channel on a current path through which the read current flows; and applying a stress on the memory cell to repair the nanowire channel of the transistor in the memory cell on the current path. The determining step can include sensing read currents of memory cells in an array of memory cells; and determining one or more memory cells in the array of memory cells having read currents below the passing criteria, using the read currents sensed.
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