Efficient bitline driven one-sided power collapse write-assist design for SRAMs
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United States of America Patent
Stats
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Jan 9, 2018
Issued Date -
N/A
app pub date -
Dec 2, 2016
filing date -
Feb 19, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.
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Patent Citation Ranking
- 1 Citation Count
- G11C Class
- 17.97 % this patent is cited more than
- 7 Age
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