One-time programmable bitcell with native anti-fuse
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Jul 27, 2017
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Jul 27, 2016
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Abstract
An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor substrate. The source is positioned over the lower doped region, and the drain is positioned over the higher doped region. A plurality of anti-fuse devices, separated from each other by a portion of the lower doped region, are each positioned at least partially above a respective portion of the source region (and, in turn, above the lower doped region). A first metal line is coupled to a first subset of the anti-fuse devices, and a second metal line is coupled to a different, second subset of the anti-fuse devices arranged between the anti-fuses in the first subset.
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