Placing and routing debugging logic
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United States of America Patent
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May 1, 2018
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N/A
app pub date -
Oct 10, 2017
filing date -
May 18, 2015
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Abstract
Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components. In another embodiment, the host system places debugging logic after placing and routing logic components of the DUT. In another embodiment, for one or more emulator FPGAs, the host system places debugging logic units of the debugging logic evenly across the FPGA before placing logic components of the DUT.
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