Architectural physical synthesis

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United States of America Patent

PATENT NO 10268797
APP PUB NO 20140082579A1
SERIAL NO

14086911

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Abstract

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Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.

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Patent Owner(s)

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SYNOPSYS INCMOUNTAIN VIEW CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Halpin, William Palo Alto, US 12 308
Lemonnier, Benoit Palo Alto, US 4 73
McElvain, Kenneth S Menlo Park, US 111 2604

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