Active trace assertion based verification system
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United States of America Patent
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Aug 6, 2019
Grant Date -
Feb 13, 2014
app pub date -
Jun 4, 2013
filing date -
Jun 16, 2006
priority date (Note) -
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status (Latency Note)
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Abstract
A method is presented for responding to user input by displaying when a circuit has a property expressed by an assertion based on data indicating values of signals of the circuit at a succession of times. The assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of times at which the expression is to be evaluated. The circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time. The method includes displaying a representation of each expression of the first sequence and identifying each variable that caused that expression to evaluate false and distinctively marking that variable's symbol relative to other variable symbols within the display for each expression of the first sequence that evaluates false at its corresponding evaluation time.
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