SYSTEM AND METHOD FOR ABSTRACTION OF A CIRCUIT PORTION OF AN INTEGRATED CIRCUIT
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United States of America Patent
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Issued Date -
Aug 20, 2015
app pub date -
Feb 14, 2014
filing date -
Feb 14, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A system, such as a computer aided design (CAD) system, is configured to abstract at least a portion of an integrated circuit (IC) design provided thereto. The system selects two signals of the IC and determines the respective sub-circuits ending at each of the signals, excluding the other sub-circuit when two sub-circuits intersect. It then identifies an intersection of the two sub-circuits and therefore establishes an abstraction therefrom. The abstraction replaces the circuit for verification purposes of the IC design. The process can repeat as may be necessary or until no two signals have sub-circuits that intersect. The process described for two signals is equally applicable to a plurality of signals for which the intersection is defined as the intersection of all the sub-circuits defined by the plurality signals. The abstraction allows for effective verification of portions of ICs as may be necessary.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SYNOPSYS INC | 675 ALMANOR AVE SUNNYVALE CA 94085 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Chakrabarti, Barsneya | Noida, IN | 5 | 9 |
Goel, Manish | Noida, IN | 105 | 1000 |
Kumar, Chandan | Ghaziabad, IN | 23 | 124 |
Movahed-Ezazi, Mohammed H | Saratoga, US | 1 | 0 |
Sarwary, Mohamed Shaker | San Diego, US | 15 | 91 |
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