SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
N/A
app pub date -
Mar 4, 2014
filing date -
Feb 13, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.
First Claim
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