NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING FOR STATIC RANDOM ACCESS MEMORY (SRAM)
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United States of America Patent
Stats
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N/A
Issued Date -
Mar 5, 2015
app pub date -
Aug 15, 2014
filing date -
Aug 27, 2013
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
In one embodiment, one portion of an SRAM array is stressed by first writing a “1” in every bit of the array, followed by an evaluation of the relevant parameters of the array using a ring oscillator driven by a mirrored bit-line current, the ring oscillator not in line of the bit-line of the SRAM. The other portion of the array is then stressed after writing a “0” in every bit of the array. The evaluation procedure is then repeated.
First Claim
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