NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING FOR STATIC RANDOM ACCESS MEMORY (SRAM)

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United States of America Patent

APP PUB NO 20150063010A1
SERIAL NO

14461338

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Abstract

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In one embodiment, one portion of an SRAM array is stressed by first writing a “1” in every bit of the array, followed by an evaluation of the relevant parameters of the array using a ring oscillator driven by a mirrored bit-line current, the ring oscillator not in line of the bit-line of the SRAM. The other portion of the array is then stressed after writing a “0” in every bit of the array. The evaluation procedure is then repeated.

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC675 ALMANOR AVE SUNNYVALE CA 94085

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
KAWA, Jamil Campbell, US 73 1110
LEUNG, Raymond Tak-Hoi Palo Alto, US 5 24
SUN, Shih-Yao Christine San Jose, US 5 21
YEH, Tzong-Kwang Henry Los Gatos, US 10 99

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