Selective Annotation Of Circuits For Efficient Formal Verification With Low Power Design Considerations
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jun 2, 2016
app pub date -
Jan 14, 2015
filing date -
Nov 30, 2014
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
Formal verification of a circuit design is performed with low power considerations. The formal verification process receives a circuit design and a low power design specification. The low power design specification identifies power domains for the circuit. The system models undefined signal reaching nodes of the circuit from components of power domains that are switched off. The system selects a subset of nodes at which undefined signal reaches, thereby excluding certain nodes from the analysis. The selection of a small subset of nodes for analyzing undefined signals increases the efficiency of the formal verification process. The system annotates the circuit design to allow undefined signals to be introduced at the selected nodes. The system performs formal verification of the annotated circuit design.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully