SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW

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United States of America Patent

SERIAL NO

14812109

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Abstract

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A system and method are provided that use pass/fail test results to prioritize electronic design verification review issues. It may prioritize either generated properties or code coverage items or both. Thus issues, whether generated properties or code coverage items, that have never been violated in any passing or failing test may be given highest priority for review, while those that have been violated in a failing test but are always valid in passing tests may be given lower priority. Still further, where end-users have marked one or more properties or code coverage items as already-reviewed, the method will give these already-reviewed issues the lowest priority. As a result, both properties and code coverage items may be generated together in a progressive manner starting earlier in development and significant duplication of effort is avoided.

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC675 ALMANOR AVENUE SUNNYVALE CA 94085

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Liu, Yong Cupertino, US 1235 24302
Lu, Yuan Saratoga, US 82 691
Yang, Jian San Jose, US 606 6431

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