PLACEMENT AND ROUTING ON A CIRCUIT
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United States of America Patent
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Issued Date -
Sep 11, 2014
app pub date -
May 19, 2014
filing date -
Jun 11, 2002
priority date (Note) -
Abandoned
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Abstract
Methods and apparatuses to place and route cells on integrated circuit chips along paths is described. In one embodiment, the method to layout an integrated circuit, the method comprises routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit, and placing a third cell of the integrated circuit after said routing the wire to connect the first cell and the second cell.
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