Isolation region fabrication for replacement gate processing
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United States of America Patent
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Oct 22, 2024
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app pub date -
Mar 22, 2021
filing date -
Mar 22, 2021
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Abstract
A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
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