Resistive memory device including reference cell to compensate for a leakage current
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United States of America
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Sep 17, 2024
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N/A
app pub date -
Oct 21, 2021
filing date -
Oct 21, 2021
priority date (Note) -
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Abstract
A resistive memory device includes a plurality of word lines, a plurality of reference cells, a plurality of first resistive memory cells, a plurality of second resistive memory cells maintained in an off state, a read circuit configured to provide a first read current to the first resistive memory cells and provide a second read current to the reference cells while one of the first resistive memory cells is selected to perform a read operation, and a compensation circuit configured to provide a compensation current based on a first leakage current from the off resistive memory cells to the reference cells to compensate for a second leakage current generated by the unselected first resistive memory cells. Each reference cell is connected to one of the word lines and each of the first resistive memory cells are connected to one of the word lines.
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