Systems and methods for minimizing static leakage of an integrated circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 26, 2021
Grant Date -
N/A
app pub date -
Mar 13, 2014
filing date -
Jul 9, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully