Forming transistor gate structures in a semiconductor using a mask layer over an insulating layer
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United States of America Patent
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Feb 5, 2019
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N/A
app pub date -
Jul 2, 2015
filing date -
Jan 30, 2009
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Abstract
A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
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