Semiconductor memory device
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United States of America Patent
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Sep 29, 2015
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N/A
app pub date -
Oct 23, 2013
filing date -
Jul 17, 1998
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Abstract
A semiconductor memory device which can reduce the size of a memory cell and increase the packing density is disclosed. Each memory cell comprises a p-type active region, an n-type active region, two word lines, a common gate line and a common gate line. Two memory cells are deviated by, for example, an amount of a half bit in the direction which perpendicularly crosses the word line direction. The memory cells are arranged with one of their parts overlapped with one another in the word line direction. Thus, the size of the memory cell can be reduced in the word line direction.
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