Semiconductor memory device
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United States of America Patent
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Apr 8, 2008
Grant Date -
N/A
app pub date -
Feb 27, 2013
filing date -
Mar 31, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar; a first second-type well including a first sense amplifying MOS transistor having a first-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar.
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