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Abstract

A channel processor capable of assigning a key code provided by a key coder and representing making (or breaking) of a key switch to one of a plurality of channels for storage therein and subsequently detecting breaking (or making) of the same key switch on the side of the channel processor. The assignment of the key code is implemented by holding the key code provided by the key coder during a predetermined period of time, detecting whether conditions for the key code assignment have been satisfied or not in a former half of the holding period and, if such conditions have been satisfied, causing the key code to be stored in an empty channel of a main memory device in a latter half of the holding period. Detection of breaking of the made key switch (or vice versa) is made by once clearing a memory storing the assigned channels by means of a start code generated by the key coder and subsequently finding that a channel among the cleared channels is not stored in the memory again, i.e., no key code assigned and stored in the main memory has been supplied from the key coder, until the time when a next start code is applied.

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First Claim