Importance

Loading Importance Indicators...

Abstract

A method and apparatus for stress testing a computer memory system is disclosed. A sequential series of bit patterns, comprising 1's and 0's, is impressedd upon a computer memory so that, during testing, every memory cell stores a 1 while the eight adjacent neighboring memory cell stores 0's. Subsequently, the complimentary bit patterns are impressed upon memory, wherein every memory cell, at some time during the test, stores a 0 while the eight immediately adjacent neighboring memory cells store 1's. The disclosed bit pattern maximizes stress on the cells, In an interleaved dual memory bank configuration, memory cells are sequentially accessed from the highest to the lowest address of one memory bank, while memory cells are sequentially accessed from the lowest to the highest memory address in the other memory bank. Toggling successive memory accesses between the dual interleaved memory banks maximizes stress on the address driver components of the computer memory system. Preferably, the dual memory banks are simultaneously tested with complementary bit patterns to also maximize stress on the data bus driver and associated components and to maximize demand on the power supply system.

Loading the Abstract Image...

First Claim