Scalable stochastic successive approximation register analog-to-digital converter
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United States of America Patent
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Jun 12, 2018
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Sep 30, 2016
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Sep 30, 2016
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Abstract
Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.
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