Method and apparatus for analog to digital error conversion with multiple symmetric transfer functions

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United States of America Patent

PATENT NO 9998135
SERIAL NO

15673234

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Abstract

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An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

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Patent Owner(s)

Patent OwnerAddress
ANDAPT HOLDINGS LTD22/28 NORTH WALL QUAY DUBLIN 1 D01 H104

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Birkner, John Woodside, US 20 192
Cheung, Herman Cupertino, US 8 14
Crotty, Patrick J San Jose, US 41 962
Samad, Maheen Sunnyvale, US 3 8
Shankar, Kapil Saratoga, US 33 768

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