MTJ memory array subgrouping method and related drive circuitry
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United States of America Patent
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Jun 12, 2018
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app pub date -
Oct 9, 2015
filing date -
Oct 9, 2015
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Abstract
Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.
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