Method of forming an interconnect structure for a semiconductor device
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United States of America Patent
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Jun 12, 2018
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N/A
app pub date -
Aug 29, 2016
filing date -
Oct 1, 2014
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Abstract
Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A spacer material layer is formed over the plurality of trenches. A via pattern including a plurality of openings is formed over the spacer material layer and plurality of trenches. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.
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