Semiconductor memory devices and methods of testing open failures thereof
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United States of America Patent
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Jun 12, 2018
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N/A
app pub date -
Mar 16, 2017
filing date -
Dec 4, 2012
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Abstract
Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. Related methods are also provided.
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