Testing retention mode of an SRAM array
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United States of America Patent
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Jun 12, 2018
Issued Date -
Feb 6, 2014
app pub date -
Aug 6, 2012
filing date -
Aug 6, 2012
priority date (Note) -
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Abstract
An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply line. During this period of time, a first current is drawn from the supply line by sources internal (i.e. leakage current) to the array. Also during this time period, current is drawn from the supply line by a discharge circuit. The second current is provided to shorten the time required to test the retention mode of the array. After the period of time has expired, the retention mode and the discharge circuit are disabled and the data pattern is read from the array and compared to the data pattern written to the array.
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