Semiconductor memory with respective power voltages for plurality of memory cells
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United States of America Patent
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Jun 12, 2018
Issued Date -
Jun 22, 2017
app pub date -
Oct 27, 2016
filing date -
Dec 17, 2015
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Abstract
A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.
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