Delay locked loop circuit including an additive delay in a command path
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United States of America Patent
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Jun 12, 2018
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N/A
app pub date -
Jan 5, 2017
filing date -
Mar 29, 2013
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Abstract
An operation control method of a semiconductor memory device includes executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal and measuring a loop delay of a DLL. The operation control method further includes storing measured loop delay information and DLL locking information; and performing a delay control of a command path using the stored loop delay information and DLL locking information independent of the DLL, during a latency control operation.
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