Nonvolatile random access memory including control circuit configured to receive commands at high and low edges of one clock cycle
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United States of America Patent
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Jun 12, 2018
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N/A
app pub date -
Feb 24, 2017
filing date -
Mar 21, 2013
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Abstract
A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.
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