Semiconductor memory device and operating method thereof
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United States of America Patent
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Jun 12, 2018
Issued Date -
Sep 14, 2017
app pub date -
Aug 23, 2016
filing date -
Mar 8, 2016
priority date (Note) -
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Abstract
In an embodiment, a semiconductor memory device may include a memory cell array, a plurality of page buffers, and a control logic. The memory cell array may include a plurality of memory cells. The plurality of page buffers may be coupled to a plurality of bit lines of the memory cell array, respectively. The control logic may control the plurality of page buffers to perform a read operation on the memory cell array. Each of the plurality of page buffers may perform data sensing by changing a voltage of a page buffer sensing signal after an internal node is precharged.
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