SMS4 acceleration processors having encryption and decryption mapped on a same hardware
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United States of America Patent
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Jun 12, 2018
Issued Date -
Dec 29, 2016
app pub date -
Jun 26, 2015
filing date -
Jun 26, 2015
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Abstract
A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a data register having a plurality of data bits and a key register having a plurality of key bits. The hardware accelerator also includes a data mode selector module to select one of an encrypt mode or a decrypt mode for processing the plurality of data bits. The hardware accelerator further includes a key mode selector module to select one of the encrypt mode or the decrypt mode for processing the plurality of key bits.
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