Stacked semiconductor package and method for performing bare die testing on a functional die in a stacked semiconductor package
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United States of America Patent
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Jun 12, 2018
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app pub date -
Mar 31, 2017
filing date -
Sep 30, 2016
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Abstract
Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.
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