Multidirectional semiconductor arrangement testing
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United States of America Patent
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Jun 12, 2018
Issued Date -
Sep 24, 2015
app pub date -
Mar 21, 2014
filing date -
Mar 21, 2014
priority date (Note) -
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Abstract
One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.
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