Yield tolerance in a neurosynaptic system
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United States of America Patent
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Jun 5, 2018
Issued Date -
Nov 3, 2016
app pub date -
Apr 25, 2014
filing date -
Apr 25, 2014
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Abstract
Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.
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