Method of optimizing CMOS IDAC linearity performance using golden ratio

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United States of America Patent

PATENT NO 9991901
APP PUB NO 20170201269A1
SERIAL NO

14844419

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Abstract

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A layout method for a current source array. A digital-to-analog converter (DAC) includes a plurality of complementary metal-oxide-semiconductor (CMOS) devices. Current sources for the CMOS devices are uniformly arranged in a one-dimensional array. The spacing between the current sources in the one-dimensional array is determined using a golden ratio.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONNEW ORCHARD ROAD ARMONK NY 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Sungjae Burlington, US 58 336

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