Phase locked loop circuit with charge pump up-down current mismatch adjustment and static phase error reduction
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United States of America Patent
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Jun 5, 2018
Issued Date -
Feb 15, 2018
app pub date -
Aug 3, 2017
filing date -
Aug 9, 2016
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Abstract
A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.
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