Dynamic current limit circuit
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United States of America Patent
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Jun 5, 2018
Issued Date -
Mar 8, 2018
app pub date -
Sep 2, 2016
filing date -
Sep 2, 2016
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Abstract
A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.
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