Self-enabled bus conflict detection circuit
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United States of America Patent
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Jun 5, 2018
Issued Date -
Dec 7, 2017
app pub date -
Oct 20, 2016
filing date -
Jun 1, 2016
priority date (Note) -
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Abstract
A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit connected to the delay unit, and a comparison unit having a first input terminal for receiving the output signal, a second terminal for receiving a reference voltage, and an enable terminal for receiving an enable signal of the duty cycle adjustment unit. The enable signal has a rising edge that is delayed relative to a rising edge of the output signal and a falling edge that is aligned with a falling edge of the output signal. The comparison unit compares a voltage level of the output signal with the reference voltage when the enable signal is in a stable voltage state and determine a bus condition in response to a comparison result.
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