Tunnel field-effect transistor (TFET) based high-density and low-power sequential
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United States of America Patent
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May 29, 2018
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Apr 27, 2017
app pub date -
Oct 23, 2015
filing date -
Oct 23, 2015
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Abstract
Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.
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