Semiconductor memory device that can stably perform writing and reading without increasing current consumption even with a low power supply voltage
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United States of America Patent
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May 29, 2018
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app pub date -
Aug 18, 2017
filing date -
May 23, 2005
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Abstract
Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.
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