Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets
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United States of America Patent
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May 29, 2018
Issued Date -
N/A
app pub date -
Nov 9, 2015
filing date -
Sep 3, 2011
priority date (Note) -
In Force
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Abstract
Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage. This approach enables programmable visual computing with throughput approaching that of hardwired solutions.

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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
MIREPLICA TECHNOLOGY LLC | 606 COQUINA LANE AUSTIN TX 78746 |
International Classification(s)

- [Classification Symbol]
- [Patents Count]
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Johnson, William M | Austin, US | 109 | 3888 |
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