Semi-data gated flop with low clock power/low internal power with minimal area overhead
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United States of America Patent
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May 22, 2018
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app pub date -
Oct 28, 2016
filing date -
Oct 28, 2016
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Abstract
Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.
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