Integrated circuit layout design methodology with process variation bands
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United States of America Patent
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May 22, 2018
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Jun 6, 2016
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May 7, 2004
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Abstract
A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.
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