Slicer and decision feedback equalization circuitry
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United States of America Patent
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May 15, 2018
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app pub date -
Mar 31, 2017
filing date -
Mar 31, 2017
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Abstract
One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.
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