Successive approximation register analog-to-digital converter
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United States of America Patent
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May 15, 2018
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Sep 25, 2017
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Sep 20, 2016
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Abstract
A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.
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