Block memory layout and architecture for programmable logic IC, and method of operating same
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United States of America Patent
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May 15, 2018
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N/A
app pub date -
Aug 18, 2016
filing date -
Sep 1, 2015
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Abstract
An integrated circuit comprising programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array, wherein each logic tile includes logic circuitry and I/O connected in an interconnect network via multiplexers. A first logic tile includes (i) a first portion of a perimeter which forms at least a portion of the periphery of the programmable/configurable logic circuitry and (ii) a second portion of a perimeter which is interior to such circuitry's periphery, wherein memory I/O is disposed on the second portion of the perimeter of the first logic tile. A second logic tile includes a second portion of a perimeter which is interior to the programmable/configurable logic circuitry's periphery and opposes the first logic tile's perimeter. Memory array(s), located between the second portions of the perimeters of the first and second logic tiles, is/are coupled to memory I/O of at least the first logic tile.
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