Method of fabricating a gate cap layer

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United States of America Patent

PATENT NO 9972498
SERIAL NO

15081932

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Abstract

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A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.

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Patent Owner(s)

Patent OwnerAddress
UNITED MICROELECTRONICS CORPHSIN-CHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hsu, Li-Chieh Taichung, TW 26 72
Huang, Po-Cheng Kaohsiung, TW 64 300
Li, Kun-Ju Tainan, TW 51 75
Li, Yu-Ting Chiayi, TW 37 177
Lin, Chih-Hsun Ping-Tung County, TW 74 301
Lin, Wen-Chin Tainan, TW 74 882
Liu, Yi-Liang Tainan, TW 13 51
Tsai, Fu-Shou Keelung, TW 23 39

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