Methods for nitride planarization using dielectric

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United States of America Patent

PATENT NO 9966272
SERIAL NO

15632931

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Abstract

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The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.

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GLOBALFOUNDRIES U S INC2600 GREAT AMERICA WAY SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chao, Tai Fong Clifton Park, US 4 20
Economikos, Laertis Wappingers Falls, US 131 1691
Huang, Haigou Rexford, US 72 574
Liu, Jinping Ballston Lake, US 60 134
Sheng, Haifeng Rexford, US 22 61
Shi, Xingzhao Clifton Park, US 5 22
Shu, Jiehui Clifton Park, US 101 232

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