A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a memory write burst command having a first frame that includes a corresponding opcode positioned in one of a first command slot or a second command slot. The memory write burst command may also include a number of subsequent frames for conveying a data payload, as specified for example, by the opcode. The control unit may be configured to generate a number of concurrent sequential memory write operations to the memory in response to receiving the memory write burst command.

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